Jiawei Liang
I’m currently a PhD candidate superivised by Professor Wei Zhang in Reconfigurable computing system laboratory (RCSL) at the Department of Electronic & Computer Engineering in HKUST. My research interests focus on hardware system and EDA for FPGA. Previously, I obtained BEng and MSc Degree in school of EE from Beihang University, China, working for CNN pruning at that time. Later, I served as an IC designer for 2 years.
Experience
Education Experience
HongKong University of Science and Technology, HongKong, China.
(2024.01 - )
Doctor of Philosophy (Ph.D.) in Electronic and Computer Engineering (ECE).
Beihang University, Beijing, China.
(2019.09 - 2022.01)
Master of Research in Electronic and Information Engineering (EE).
Beihang University, Beijing, China.
(2015.09 - 2019.07)
Bachelor of Engineering (B.Eng.) in Electronic and Information Engineer (EE).
Industrial Experience
Zeku Tech., Beijing, China.
(2022.02 - 2023.05)
- Served as a Modem PHY IC designer, worked for 4/5G uplink channel encoder (TX ENC), FFT, 23G DMA pre-process module design, and some common IP were designed such as pipo-based pseudo double port SRAM interface, FIFO based PIPE module.
- Unforgettable Memories: I have completed the first ECO in my department, and I have complated totally three ECO T_T.
- In last year rating, I get “Outstanding” (Top 10%)^_^
NVIDIA Tech., Beijing, China.
(2021.07 - 2021.09)
- Served as a Physical Design intern, worked for clock skew analyzing in module level.
- An interesting tool was developed for visualization of clock skews.
Teaching Experience
ELEC 3300, Introduction to Embedded Systems
School of Engineering, Department of ECE, HKUST. (2025.02 - 2024.05)
- Served as an TA.
ELEC 4320, FPGA-based Design: From Theory to Practice, Autumn
School of Engineering, Department of ECE, HKUST. (2024.09 - 2024.11)
- Served as an TA.
Digital Signal Processing, Autumn
Department of EE, BUAA. (2020.09 - 2021.01)
- Served as an TA.
Electronic Design, Summer
Department of EE, BUAA. (2020.07 - 2020.09)
- Served as an TA. An FPGA based CNN accelerator is designed as an exp for it and the reference code and tutorial (in Chinese) are published.
Publication
Journal
[J3] He Li, Jiawei Liang, Hongxiang Fan, “Design space exploration for efficient quantum most-significant digit-first arithmetic”, IEEE Transactions on Computers (TC), 2022. pdf code
[J2] Pei Lei, Jiawei Liang, Tong Zheng, Jun Wang, “Design space exploration for efficient quantum most-significant digit-first arithmetic”, IEEE Transactions on Neural Network and Learning System (TNNLS), 2022. pdf
[J1] Peng Lei, Jiawei Liang, Zhenyu Guan, Jun Wang, Tong Zheng, “Acceleration of FPGA based convolutional neural network for human activity classification using millimeter-wave radar”, IEEE ACCESS, 2019. pdb
Conference
[C6] Linfeng Du, Jiawei Liang, Jason Lau, Yuze Chi, Yutong Xie, Chunyou SU, Afzal Ahmad, Zifan He, Jake Ke, Jinming Ge, Jason Cong, Wei Zhang and Licheng Guo. “Automated Design Space Exploration in High-Level Physical Synthesis.” Proceedings of the 44th IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 2025.
[C5] Zeyu Li, Shangkun Li, Chuyi Dai, Chaofang Ma, Jiawei Liang, Xin Li and Wei Zhang, “Robin: RWKV accelerator using Block Circulant Matrices based on FPGA”, Proceedings of the 44th IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 2025.
[C4] Xingyu Liu, Jiawei Liang, Linfeng Du, Yipu Zhang, Hanwei Fan, Chaofang Ma, Jiang Xu, Wei Zhang, “FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration”, 54th International Conference on Parallel Processing (ICPP), 2025.
[C3] Jiawei Liang, Linfeng Du, Xiaofeng Zhou, Zhe Lin, Jiang Xu, Wei Zhang, “AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs”, 62th ACM/IEEE Design Automation Conference (DAC), 2025. code
[C2] Yipu Zhang, Jiawei Liang, Jian Peng, Jiang Xu, Wei Zhang, “SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2025. pdf
[C1] He Li, Hongxiang Fan, Jiawei Liang, “Quantum most-significant digit-first addition”, 12th International Green and Sustainable Computing Conference (IGSC), 2021. pdf