Jiawei Liang

I am a Ph.D. candidate supervised by Professor Wei Zhang in the Reconfigurable Computing Systems Laboratory (RCSL) at the Department of Electronic and Computer Engineering, HKUST. My research interests focus on hardware systems and EDA for FPGA.

Previously, I obtained my B.Eng. and M.Sc. degrees from the School of Electronic and Information Engineering at Beihang University, China, where I worked on CNN pruning. I also served as an IC designer for two years.

Hardware Systems Reconfigurable Computing FPGA & EDA

Experience

Education

Hong Kong University of Science and Technology, Hong Kong, China

2024.01 - Present

Doctor of Philosophy (Ph.D.) in Electronic and Computer Engineering (ECE).

Beihang University, Beijing, China

2019.09 - 2022.01

Master of Research in Electronic and Information Engineering (EE).

Beihang University, Beijing, China

2015.09 - 2019.07

Bachelor of Engineering (B.Eng.) in Electronic and Information Engineering (EE).

Industry

Zeku Tech., Beijing, China

2022.02 - 2023.05

  • Served as a Modem PHY IC designer, working on the 4/5G uplink channel encoder (TX ENC), FFT, 23G DMA pre-process module design, and common IP including a PIPO-based pseudo dual-port SRAM interface and a FIFO-based PIPE module.
  • Completed the first ECO in my department and completed three ECOs in total.
  • Received an “Outstanding” rating, Top 10%.

NVIDIA Tech., Beijing, China

2021.07 - 2021.09

  • Served as a Physical Design intern, working on module-level clock skew analysis.
  • Developed a visualization tool for clock skews.

Teaching

ELEC 4320, FPGA-based Design: From Theory to Practice

School of Engineering, Department of ECE, HKUST. 2024.09 - 2024.11

  • Served as a TA.

ELEC 3300, Introduction to Embedded Systems

School of Engineering, Department of ECE, HKUST. 2025.02 - 2025.05

  • Served as a TA.

ELEC 4320, FPGA-based Design: From Theory to Practice

School of Engineering, Department of ECE, HKUST. 2024.09 - 2024.11

  • Served as a TA.

Digital Signal Processing

Department of EE, BUAA. 2020.09 - 2021.01

  • Served as a TA.

Electronic Design

Department of EE, BUAA. 2020.07 - 2020.09

  • Served as a TA. An FPGA-based CNN accelerator was designed as an experiment for the course, and the reference code and tutorial were published in Chinese.

Publications

View Google Scholar profile

Journal

  • [J3] Pei Lei, Jiawei Liang, Tong Zheng, Jun Wang, “Design space exploration for efficient quantum most-significant digit-first arithmetic”, IEEE Transactions on Neural Network and Learning System (TNNLS), 2024. [DOI](https://ieeexplore.ieee.org/abstract/document/9881223/)
  • [J2] He Li, Jiawei Liang, Hongxiang Fan, Yongming Tang, “Design space exploration for efficient quantum most-significant digit-first arithmetic”, IEEE Transactions on Computers (TC), 2023. [DOI](https://ieeexplore.ieee.org/abstract/document/9924609/) code
  • [J1] Peng Lei, Jiawei Liang, Zhenyu Guan, Jun Wang, Tong Zheng, “Acceleration of FPGA based convolutional neural network for human activity classification using millimeter-wave radar”, IEEE Access, 2019. [DOI](https://ieeexplore.ieee.org/abstract/document/8753553/)

Conference

  • [C9] Shangkun Li, Jinming Ge, Diyuan Tao, Zeyu Li, Jiawei Liang, Linfeng Du, Jiang Xu, Wei Zhang, and Cheng Tan. “NEURA: A Unified and Retargetable Compilation Framework for Coarse-Grained Reconfigurable Architectures”, PLDI, 2026. [DOI](https://dl.acm.org/doi/abs/10.1145/3808285)
  • [C8] Shangkun Li, Cheng Tan, Zeyu Li, Jinming Ge, Jiawei Liang, Hao Yang, Linfeng Du, Jiang Xu, Wei Zhang. “A Cluster-Based Distributed Memory Architecture for CGRAs”, DATE, 2026. [DOI](https://ieeexplore.ieee.org/abstract/document/11539358)
  • [C7] Xingyu Liu, Jiawei Liang, Yipu Zhang, Linfeng Du, Chaofang Ma, Hui Yu, Jiang Xu and Wei Zhang. “DRACO: A Hardware-Efficient Robot Rigid Body Dynamics Accelerator with Precision-Aware Quantization Framework”, HPCA, 2026. [DOI](https://ieeexplore.ieee.org/abstract/document/11408528)
  • [C6] Linfeng Du, Jiawei Liang, Jason Lau, Yuze Chi, Yutong Xie, Chunyou Su, Afzal Ahmad, Zifan He, Jake Ke, Jinming Ge, Jason Cong, Wei Zhang and Licheng Guo. “Automated Design Space Exploration in High-Level Physical Synthesis”, Proceedings of the 44th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025. [DOI](https://ieeexplore.ieee.org/abstract/document/11240757)
  • [C5] Zeyu Li, Shangkun Li, Chuyi Dai, Chaofang Ma, Jiawei Liang, Xin Li and Wei Zhang, “Robin: RWKV accelerator using Block Circulant Matrices based on FPGA”, Proceedings of the 44th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025. [DOI](https://ieeexplore.ieee.org/abstract/document/11240845/)
  • [C4] Xingyu Liu, Jiawei Liang, Linfeng Du, Yipu Zhang, Hanwei Fan, Chaofang Ma, Jiang Xu, Wei Zhang, “FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration”, 54th International Conference on Parallel Processing (ICPP), 2025. [DOI](https://dl.acm.org/doi/pdf/10.1145/3754598.3754629)
  • [C3] Jiawei Liang, Linfeng Du, Xiaofeng Zhou, Zhe Lin, Jiang Xu, Wei Zhang, “AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs”, 62nd ACM/IEEE Design Automation Conference (DAC), 2025. [DOI](https://ieeexplore.ieee.org/abstract/document/11133279/) code
  • [C2] Yipu Zhang, Jiawei Liang, Jian Peng, Jiang Xu, Wei Zhang, “SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2025. [DOI](https://ieeexplore.ieee.org/abstract/document/10992839/)
  • [C1] He Li, Hongxiang Fan, Jiawei Liang, “Quantum most-significant digit-first addition”, 12th International Green and Sustainable Computing Conference (IGSC), 2021. [DOI](https://ieeexplore.ieee.org/abstract/document/9651595/)